搜索结果: 1-15 共查到“信息处理技术 architecture”相关记录19条 . 查询时间(0.14 秒)
An image sensor comprising an array of apertures each with its own local integrated optics and pixel array is presented. A lens focuses the image above the sensor creating overlapping elds of view bet...
Multiple Capture Single Image Architecture with a CMOS Sensor
Multiple Capture Single Image Architecture CMOS Sensor
2015/8/17
We describe a programmable digital camera sensor with pixel-level analog-to-digital conversion (ADC). The sensor, which was designed and implemented by our group, is programmable in the sense that the...
GPS Receiver Architecture Effects on Controlled Reception Pattern Antennas for JPALS
GPS Receiver Architecture Effects Controlled Reception Pattern Antennas JPALS
2015/6/26
Stanford University is developing a controlled reception pattern antenna (CRPA) array with beam research testbed to evaluate CRPA algorithms and software tools, and their effects on GPS signals and sa...
A single-photon sampling architecture for solid-state imaging sensors
A single-photon sampling architecture solid-state imaging sensors
2015/6/17
Advances in solid-state technology have enabled the development of silicon photomultiplier sensor arrays capable of sensing individual photons. Combined with high-frequency time-todigital converters (...
Efficient Macroblock Pipeline Structure in High Definition AVS Video Encoder VLSI Architecture
Efficient Macroblock Pipeline Structure AVS Video Encoder VLSI Architecture
2010/12/21
In traditional four-stage pipeline structures for H.264 video encoder hardware implementation, rate distortion optimization (RDO) based mode decision was turned off, and
dual-port or ping-pang on-chi...
High Throughput VLSI Architecture for Multiresolution Motion Estimation in High Definition AVS Video Encoder
VLSI Architecture Multiresolution Motion Estimation Video Encoder
2010/12/21
This paper proposes a hardware friendly multiresolution motion estimation algorithm and VLSI architecture for high definition MPEG-like video encoder hardware implementation. By parallel searching and...
A Novel VLSI Architecture of Motion Compensation for Multiple Standards
VLSI Architecture Motion Compensation Multiple Standards
2010/12/17
Motion compensation (MC) is one of the most important technologies capable of removing the temporal redundancy and widely adopted by the main video standards. From the older MPEG-2 to the latest H.264...
In AVS-P2 video compression standard, similar to MPEG-2, entropy coding firstly assembles two
dimensional coefficients of each block into a sequence of (Run, Level) combinations serially. As we know,...
Reusable Architecture and Complexity-Controllable Algorithm for the Integer/Fractional Motion Estimation of H.264,
Reusable Architecture Complexity-Controllable Algorithm Integer/Fractional Motion Estimation
2010/12/16
Motion estimation is the most computational intensive part of H.264 video coding. The motion estimation of H.264 includes int eger motion estimation and fractional motion estimation. In this paper, a ...
A DRM architecture for manageable P2P based IPTV system
DRM architecture manageable P2P IPTV system
2010/12/17
With the improvement of network bandwidth, multimedia services based on streaming live media have gained much attention recently, among which IPTV has become a hot topic. After emergence of Peer-to-Pe...
A Motion Vector Predictor Architecture for AVS and MPEG-2 HDTV Decoder,
Motion compensation Motion vector prediction AVS MPEG
2010/12/16
In the advanced Audio Video coding Standard (AVS), many efficient coding tools are adopted in motion compensation, such as new motion vector prediction, direct mode matching, variable block-sizes etc....
An Efficient VLSI Architecture for Motion Compensation of AVS HDTV Decoder
VLSI Architecture Motion Compensation AVS HDTV Decoder
2010/12/16
An Efficient VLSI Architecture for Motion Compensation of AVS HDTV Decoder.
An Efficient VLSI Architecture of VLD for AVS HDTV Decoder
VLSI Architecture VLD AVS HDTV Decoder
2010/12/16
!aIn this paper, we present a VLSI design of Variable Length Code Decoder for AVS video standard. As a co-processor of a RISC CPU, the design can decode Fixed Length Code, unsigned or signed k-th Exp-...
An Implemented VLSI Architecture of Inverse Quantizer for AVS HDTV Video Decoder
VLSI Architecture Inverse Quantizer AVS HDTV Video Decoder
2010/12/15
AVS is Chinese new audio and video coding standard. A pipeline-based architecture of inverse quantizer for AVS video standard is proposed in this paper. Due to using one-pass processing for Run Length...
Improved FFSBM Algorithm and Its VLSI Architecture for Variable Block Size Motion Estimation of H.264,
Improved FFSBM Algorithm VLSI Architecture Variable
2010/12/15
The video coding standard H.264/AVC has adopted variable block size motion estimation to improve coding efficiency, which has brought heavy computation burden.The FFSBM (fast full search block matchin...